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high voltage latch-up proof, dual spdt switches data sheet adg5236 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features latch-up proof 2.5 pf off source capacitance 12 pf off drain capacitance ?0.6 pc charge injection low leakage: 0.4 na maximum at 85c 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagrams adg5236 s1a s1b in1 s2a s2b in2 d1 d2 switches shown for a logic 1 input. 09769-001 figure 1. tssop package adg5236 s2a d2 s2b s1a d1 s1b in2 en in1 logic switches shown for a logic 1 input. 09769-002 figure 2. lfcsp package general description the adg5236 is a monolithic cmos device containing two independently selectable single-pole/double throw (spdt) switches. an en input on the lfcsp package enables or disables the device. when disabled, all channels switch off. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. both switches exhibit break-before-make switching action for use in multiplexer applications. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed together with high signal bandwidth make the device suitable for video signal switching. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors thereby preventing latch-up even under severe overvoltage conditions. 2. ultralow capacitance and <1 pc charge injection. 3. dual-supply operation. for applications where the analog signal is bipolar, the adg5236 can be operated from dual supplies up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the adg5236 can be operated from a single rail power supply up to 40 v. 5. 3 v logic-compatible digital inputs. v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
adg5236 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or dx ............................. 7 absolute maximum ratings ............................................................8 esd caution ...................................................................................8 pin configurations and function descriptions ............................9 truth tables for switches .............................................................9 typical performance characteristics ........................................... 10 test circuits ..................................................................................... 14 terminology .................................................................................... 16 trench isolation .............................................................................. 17 applications information .............................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 4/12 rev. 0 to rev. a updated outline dimensions ....................................................... 1 9 changes to ordering guide .......................................................... 1 9 7 / 1 1 r ev ision 0: initial version
data sheet adg5236 rev. a | page 3 of 20 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog sw itch analog signal range v dd to v ss v max on resistance, r on 160 ? typ v s = 10 v, i s = ?1 ma , see figure 25 200 250 280 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels , ? r on 1.4 ? typ v s = 10 v , i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 38 ? typ v s = 10 v, i s = ?1 ma 50 65 70 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.01 na typ v s = 10 v, v d = ? 10 v , see figure 27 0.1 0. 2 0.4 na max drain off leakage, i d (off ) 0.01 na typ v s = 10 v, v d = ? 10 v , see figure 27 0.1 0. 4 1.2 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 10 v , see figure 24 0.2 0.4 1.2 na max digital inputs input high voltage, v inh 2.0 v min input lo w voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 150 ns typ r l = 300 ?, c l = 35 pf 230 280 315 ns max v s = 10 v , see figure 30 t on 170 ns typ r l = 300 ?, c l = 35 pf 215 265 300 ns max v s = 10 v , see figure 32 t off 160 ns typ r l = 300 ?, c l = 35 pf 185 205 225 ns max v s = 10 v , see figure 32 break - before - make time delay, t d 75 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v , see figur e 31 charge injection, q inj ? 0.6 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf , see figure 33 off isolation ? 85 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz , see figure 28 c hannel - to - channel crosstalk ? 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz , see figure 26 ?3 db bandwidth 266 mhz typ r l = 50 ?, c l = 5 pf , see figure 29 insertion l oss ? 7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 29 c s (off ) 2.5 pf typ v s = 0 v, f = 1 mhz c d (off ) 12 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 0 v, f = 1 mhz
adg5236 data sheet rev. a | page 4 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power re quirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v s s = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v max on resistance, r on 140 ? typ v s = 15 v, i s = ?1 ma , see figure 25 160 200 230 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 1. 3 ? typ v s = 15 v , i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 33 ? typ v s = 15 v, i s = ?1 ma 45 55 60 ? max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.01 na typ v s = 15 v, v d = ? 15 v , see figu re 27 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.01 na typ v s = 15 v, v d = ? 15 v , see figure 27 0.1 0.4 1.2 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 15 v , see figure 24 0.2 0.4 1.2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 150 ns typ r l = 300 ?, c l = 35 pf 210 260 290 ns max v s = 10 v , see figure 30 t on 150 ns typ r l = 300 ?, c l = 35 pf 190 235 267 ns max v s = 10 v , see figure 32 t off 155 ns typ r l = 300 ?, c l = 35 pf 180 200 215 ns max v s = 10 v , see f igure 32 break - before - make time delay, t d 60 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v , see figure 31 charge injection, q inj ? 0.6 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf , see figure 33 off isolation ?85 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 28 channel - to - channel crosstalk ?85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz , see figure 26 ?3 db bandwidth 266 mhz typ r l = 50 ?, c l = 5 pf , see figure 29 insertion loss ?7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 29
data sheet adg5236 rev. a | page 5 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments c s (off ) 2.5 pf typ v s = 0 v, f = 1 mhz c d (off ) 12 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ?40 c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 350 ? typ v s = 0 v to 10 v, i s = ?1 ma , see figure 25 500 610 700 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 3 ? typ v s = 0 v to 10 v, i s = ?1 ma 20 21 22 ? max on - resistance flatness, r flat (on) 1 45 ? typ v s = 0 v to 10 v, i s = ?1 ma 280 335 370 ? max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.01 na typ v s = 1 v/10 v, v d = 10 v/ 1 v , s ee figure 27 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.01 na typ v s = 1 v/10 v, v d = 10 v/ 1 v , see figure 27 0.1 0.4 1.2 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 1 v/10 v , see figure 24 0.2 0.4 1.2 na max digital inputs i nput high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 220 ns typ r l = 300 ?, c l = 35 pf 390 430 490 ns max v s = 8 v , see figure 30 t on 275 ns typ r l = 300 ? , c l = 35 pf 380 440 510 ns max v s = 8 v , see figure 32 t off 160 ns typ r l = 300 ? , c l = 35 pf 195 225 245 ns max v s = 8 v , see figure 32 break - before - make time delay, t d 145 ns typ r l = 300 ? , c l = 35 pf 65 ns min v s1 = v s2 = 8 v , see figure 31 charge injection, q inj ? 0.6 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf , see figure 33
adg5236 data sheet rev. a | page 6 of 20 parameter 25c ?40 c to +85c ?40c to +125c unit test conditions/comments off isolation ?90 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 28 channel - to - channel crosstalk ?90 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz , see figure 26 ?3 db bandwidth 185 mhz typ r l = 50 ? , c l = 5 pf , see figure 29 insertion loss ?11 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 29 c s (off ) 3 pf typ v s = 6 v, f = 1 mhz c d (off ) 16 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 16 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 65 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 150 ? typ v s = 0 v to 30 v, i s = ?1 ma , see figure 25 170 215 245 ? max v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 1. 4 ? typ v s = 0 v to 30 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat(on) 35 ? typ v s = 0 v to 30 v, i s = ?1 ma 50 60 65 ? max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v , see figure 27 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v , se e figure 27 0.1 0.4 1.2 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 1 v/30 v , see figure 24 0.2 0.4 1.2 na max digital inputs inp ut high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t tr ansition 180 ns typ r l = 300 ?, c l = 35 pf 250 275 305 ns max v s = 18 v , see figure 30 t on 170 ns typ r l = 300 ? , c l = 35 pf 225 265 295 ns max v s = 18 v , see figure 32
data sheet adg5236 rev. a | page 7 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments t off 170 ns typ r l = 300 ? , c l = 35 pf 215 215 225 ns max v s = 18 v , see figure 32 break - before - make time delay, t d 75 ns typ r l = 300 ? , c l = 35 pf 35 ns min v s1 = v s2 = 18 v , see figure 31 charge injection, q inj ? 0.6 pc typ v s = 18 v, r s = 0 ? , c l = 1 nf , see figure 33 off isolation ?85 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 28 channel - to - channel crosstalk ?85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz , see figure 26 ?3 db bandwidth 266 mhz typ r l = 50 ? , c l = 5 pf , see fig ure 29 insertion loss ?7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz , see figure 29 c s (off ) 2.5 pf typ v s = 18 v, f = 1 mhz c d (off ) 12 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 15 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 8 5 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subje ct to production test. continuous current p er channel, s x a, sxb, or dx table 5 . paramet er 25c 85c 125c unit continuous current, s x a, sxb, or d x v dd = + 1 5 v, v ss = ?1 5 v tssop ( ja = 1 12.6 c/w ) 19 7 2.8 ma max lfcsp ( ja = 30.4 c/w ) 30 7.7 2.8 ma max v dd = + 20 v, v ss = ?20 v tssop ( ja = 1 12.6 c/w ) 21 7 2.8 ma max lfcsp ( ja = 30.4 c/w ) 31 7.7 2.8 ma max v dd = 12 v, v ss = 0 v tssop ( ja = 1 12.6 c/w ) 14 6.3 2.7 ma max lfcsp ( ja = 30.4 c/w ) 22.5 7.3 2.8 ma max v dd = 36 v, v ss = 0 v tssop ( ja = 1 12.6 c/w ) 24 7.4 2.8 ma max lfcsp ( ja = 30.4 c/w ) 35 7.8 2.8 ma max
adg5236 data sheet rev. a | page 8 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6 . parameter rating v dd to v ss 4 8 v v dd to gnd ?0.3 v to + 4 8 v v ss to gnd +0.3 v to ? 4 8 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx a, sxb, or dx pin 63 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current , sx a, sxb, or d x 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop ( 4 - layer board) 112c/w 16- lead lfcsp 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. th is is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. only one absolute maximum rating can be applied at any one time. esd caution 1 overvoltages at the in x , sx a, sxb , and d x pins are clamped by internal diodes. limit the c urrent to the maximum ratings given. 2 see table 5 .
data sheet adg5236 rev. a | page 9 of 20 pin configurations a nd function descript ions in1 1 s1a 2 d1 3 s1b 4 nc 16 nc 15 nc 14 v dd 13 v ss 5 s2b 12 gnd 6 d2 11 nc 7 s2a 10 nc 8 in2 9 nc = no connect adg5236 top view (not to scale) 09769-003 figure 3. tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. 1 d1 2 s1b 3 v ss 4 gnd 11 v dd 12 en 10 s2b 9 d2 5 nc 6 in2 7 nc 8 s2a 15 in1 16 s1a 14 nc 13 nc top view (not to scale) adg5236 09769-004 figure 4 . lfcsp pin configuration table 7 . pin function descriptions pin no. tssop lfcsp neonic description 1 15 in1 logic control input 1 . 2 16 s1a source terminal 1 a . this pin c an be an input or output. 3 1 d1 drain terminal 1 . this pin c an be an input or output. 4 2 s1b source terminal 1 b . this pin c an be an input or output. 5 3 v ss most negative power supply potential. 6 4 gnd ground (0 v) reference. 7, 8, 14 to 16 5, 7, 13, 14 nc no connect. these pins are open. 9 6 in2 logic control input 2 . 10 8 s2a source terminal 2 a . this pin c an be an input or output. 11 9 d2 drain terminal 2 . this pin c an be an input or output. 12 10 s2b source terminal 2 b . this pin c an be an input or output. 13 11 v dd most positive power supply potential. n/a 1 12 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, the inx logic inputs determine the on switches. n/a 1 ep exposed pad exposed pad . the exposed pad is connected internally. for increased reliability of the solder joints and m aximum thermal capability, it is recommended that the pad be soldered to the substr ate, v ss . 1 n/a means not applicable. truth table s f or switches table 8 . tssop truth table in sa sb 0 off on 1 on off table 9 . lfcsp truth table n in sa sb 0 x 1 off off 1 0 off on 1 1 on off 1 x means dont care.
adg5236 data sheet rev. a | page 10 of 20 typical performance characteristics 160 0 20 40 60 80 100 120 140 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance (?) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09769-105 figure 5 . on resistance vs. v s , v d ( dual supply ) 250 200 150 100 50 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance (?) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +13.2v v ss = ?13.2v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09769-106 figure 6. on resistance vs. v s , v d ( dual supply ) 500 450 400 350 300 250 200 150 100 50 0 0 14 12 10 8 6 4 2 on resistance (?) v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09769-107 figure 7. on resistance vs. v s , v d (single supply ) 160 140 120 100 80 60 40 20 0 0 40 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v 09769-108 figure 8. on resistance vs. v s , v d (single supply ) 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 on resistance (?) v s , v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09769-109 figure 9 . on resistance vs. v d or v s f or different temperatures, 15 v dual supply 200 160 120 80 40 180 140 100 60 20 0 ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance (?) v s , v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09769- 1 10 figure 10 . on resistance vs. v d or v s for different temperatures, 20 v dual supply
data sheet adg5236 rev. a | page 1 1 of 20 500 400 300 200 100 450 340 250 150 50 0 0 2 4 6 8 10 12 on resistance (?) v s , v d (v) v dd = 12v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09769- 11 1 figure 11 . on resistance vs. v d or v s for different temperatures, 1 2 v single supply 250 200 100 150 50 0 0 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09769- 1 12 figure 12 . on resistance vs. v s or v d for different temperatures, 36 v single supply 10 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 20 40 60 80 100 120 leakage current (pa) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09769- 1 13 figure 13 . leakage current vs. temperature , 1 5 v dual supply 0 20 40 60 80 100 120 temperature (c) 100 ?200 ?150 ?100 ?50 0 50 leakage current (pa) v dd = +20v v ss = ?20v v bias = +15v/?15v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09769- 1 14 figure 14 . leakage current vs. temperature , 20 v single supply 0 20 40 60 80 100 120 temperature (c) 40 20 ?120 ?100 ?80 ?60 ?40 ?20 0 leakage current (pa) v dd = 12v v ss = 0v v bias = 1v/10v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09769- 1 15 figure 15 . leakage current vs. temperature, 12 v single supply 0 20 40 60 80 100 120 temperature (c) 50 ?250 ?200 ?150 ?100 ?50 0 leakage current (pa) v dd = 36v v ss = 0v v bias = 1v/30v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09769- 1 16 figure 16 . leakage current vs. temperature, 36 v single supply
adg5236 data sheet rev. a | page 12 of 20 10k 100k 1m 10m 100m 1g frequency (hz) 0 ?120 ?100 ?80 ?60 ?40 ?20 i l (db) t a = 25c v dd = +15v v ss = ?15v 09769-117 figure 17 . off isolation vs. frequency 10k 100k 1m 10m 100m 1g frequency (hz) 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 crosstalk (db) t a = 25c v dd = +15v v ss = ?15v between sa and sb between s1 and s2 09769- 1 18 figure 18 . crosstalk vs. frequency ?20 ?10 0 10 20 30 40 v s (v) 1.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 charge injection (pc) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09769- 1 19 figure 19 . charge injection vs. source voltage 1k 10k 100k 1m 10m frequency (hz) 0 ?120 ?100 ?80 ?60 ?40 ?20 acpsrr (db) t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09769-120 figure 20 . acpsrr vs. frequ ency 100k 1m 10m 100m 1g frequency (hz) 0 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 attenuation (db) t a = 25c v dd = +15v v ss = ?15v 09769-122 figure 21 . bandwidth 350 300 250 200 150 100 50 0 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) v dd = +12v v ss = 0v v dd = +36v v ss = 0v v dd = +15v v ss = ?15v v dd = +20v v ss = ?20v 09769-123 figure 22 . t transition time vs. temperature
data sheet adg5236 rev. a | page 13 of 20 ?15 ?10 ?5 0 5 10 15 v s (v) 0 5 10 15 20 capacitance (pf) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09769-124 figure 23 . capacitance vs. source voltage, dual supply
adg5236 data sheet rev. a | page 14 of 20 test circuits sxa/sxb dx a v d i d (on) nc nc = no connect 09769-025 figure 24. on leakage i ds sxa/sxb dx v s v 09769-023 figure 25. on resistance channel-to-channel crosstalk = 20 log v out gnd sxa dx sxb v out network analyzer r l 50 ? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss inx 09769-032 figure 26. channel-to-channel crosstalk sxa/sxb dx v s a a v d i s (off) i d (off) 09769-024 figure 27. off leakage v out 50 ? network analyzer r l 50 ? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? nc sxb off isolation = 20 log v out v s 09769-030 figure 28. off isolation v out 50 ? network analyzer r l 50 ? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb insertion loss = 20 log v out with switch v out without switch 09769-031 figure 29. bandwidth
data sheet adg5236 rev. a | page 15 of 20 inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 ? 50% 50% 90% 50% 50% 90% t on transition t off transition v in v out v in 09769-026 figure 30. switching times inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300? 80% t d t d v out v in 09769-027 figure 31. break-before-make time delay t d output inx 50? 300 ? gnd sxa sxb dx 35pf v in en v dd v ss v dd v ss v s 3v 0v output 50% 50% t off (en) t on (en) 0.9v out 0.1v out enable drive (v in ) 09769-028 figure 32. enable delay, t on (en), t off (en) v in (normally closed switch) v out v in (normally open switch) off ? v out on q inj = c l ? v out inx v out dx sxa v dd v ss v dd v ss gnd c l 1nf nc sxb v in v s 0.1f 0.1f 09769-029 figure 33. charge injection
adg5236 data sheet rev. a | page 16 of 20 terminology i dd i dd represents t he positive supply current. i ss i ss represents t he negative supply current. v d , v s v d and v s represent t he analog voltage on terminal d and terminal s , respectively . r on r on represents t he ohmic resistance between terminal d and terminal s. ? r on ? r on represents the difference between the r on of any two channels . r flat (on) f latness that is defined as the difference between the maximum and minimum val ue of on resistance measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is t he source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent t he channel leakage current s with the switch on. v inl v inl is t he maximum input voltage for logic 0. v inh v inh is t he minimum input voltage for logic 1. i inl , i inh i inl and i inh represent t he low and high input current s of the digital input s. c d (off) c d (off) represents t he off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents t he off switch source capacitance, which is measured with reference to ground. c d (on), c s ( on) c d (on) and c s (on) represent on switch capacitance s , which are measured with reference to ground. c in c in is t he digital input capacitance. t on t on represents t he delay between applying the digital control input and the output switching on . t off t off represents t he delay between applying the digital control input and the output switching off. t d t d represents the o ff time measured between the 80% point of both switches when switching from one address state to another. off isolation off isola tion is a measure of unwanted signal coupling through an off switch. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwan ted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is the frequency at which the output is attenuated by 3 db. on response on response is t he frequency response of the on switch. in sertion loss insertion loss is t he loss due to the on resistance of the switch. ac power supply rejection ratio (acpsrr) acpsrr is t he ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p.
data sheet adg5236 rev. a | page 17 of 20 trench isolation in the adg5236 , an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a co mpletely latch - up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltage conditions, this diode can become forward - biased. a silicon co ntrolled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that , in turn, leads to latch - up. with trench isolation, this diode is removed, and the result is a latch - up proof switch. nmos pmos p well n well buried oxide layer handle wafer trench 09769-045 figure 34 . trench isolation
adg5236 data sheet rev. a | page 18 of 20 applications informa tion the adg5 2 xx family of switches and multiplexers provide a robust solution for instrumentation, i ndustrial, automotive, aerospace , and other harsh environments that are prone to latc h - up, which is an undesirable high current state that can lead to device failure and persist s until t he power supply is turned off. the adg5236 high voltage switches allow single - supply operation from 9 v to 4 0 v and dual supply operation from 9 v to 22 v.
data sheet adg5236 rev. a | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 35. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 36. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5236bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG5236BRUZ-RL7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5236bcpz-rl7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-17 1 z = rohs compliant part.
adg5236 data sheet rev. a | page 20 of 20 notes ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09769-0-4/12(a)

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